In a network on a chip device, a plurality of processing elements write data to memory that supports random access by sending a write packet to a memory controller of the memory, where each of the write packets includes respective write data and a respective memory address where the write data is to be written, also referred to as a write address. In order for write data to be written by a processing element to the memory in an aggregated manner, a memory address that is currently available for writing—i.e., one that is contiguous to the last used memory address to which other write data has been previously written—must be known by the processing element at the time when it transmits to the memory controller a write packet with the write data. The last used memory address to which the other write data had been previously written can be obtained by the processing element through a notification sent by the memory controller or by another processing element that has written the other write data to the last used memory address.